The demand for cell phones, PDAs, digital cameras and other electronic devices to be smaller, lighter and more powerful has driven the development of more compact electronic memory device packaging with increased functionality. Stacked die packages include two or more die that are placed on top of each other and are fitted into the same area. Stacked-die packages are often used in products requiring increased memory density and performance in a reduced package size. Within a stacked die memory component, each die in the stack must be individually activated or selected to properly assign various contacts and control pins, such as a DQ pad, a command pad, a chip select pin, and a clock enable pin. Conventionally, the stacked dies are selectively assigned through built-in fuses and antifuses that are programmed before the dies are packaged.
For example, in preparing die for use in a dual die-stack device, die are designated as either a “top” die or a “bottom” die while still in wafer form. Designating devices as either top or bottom die prior to assembly, however, can cause the stacking assembly process to be costly and inefficient. Additionally, each die must be sorted and tracked separately to be paired accordingly, further complicating the assembly process which may add to the cost of manufacturing stacked die devices.
After the die have been designated a stack position and prior to bonding a top die and a bottom die, the die undergo a variety of testing to identify the “good” dies for packaging and the “bad” dies to discard. The good top and bottom die go on to be paired together and packaged. A problem that can result is that the number of good top dies are not equal to the number of good bottom die. As a result, the extra top or bottom dies remain unpaired and may be used in monolithic integrated circuits. However, the bonding configurations would have to be changed from the current stack assignments to match the monolithic configuration, adding steps to the overall assembly process. Stacked die assembly processes are designed to maximize productivity and assembly yield while minimizing yield loss and development time to assemble the completed package.
There is, therefore, a need for programming stack positions of die in multi-die memory devices after packaging.